Case study

Z80 NMOS Silicon-to-RTL CPU Core: reconstructing transistor logic in Verilog

Z80 NMOS Silicon-to-RTL CPU Core reconstructs the Zilog NMOS Z80 processor as synchronous Verilog from a transistor-level netlist and successive logic schematics. The author reports testing a Verilator model with Z80 software suites in EmuStudio.

Targets: Firmware
Category: Independent reconstruction cases
Relationship: Independent reconstruction project
Sources reviewed: 2026-11-06
Evidence class: C2 code & docs, no demo or download

Stars: 13
Last commit: 2026-10-07
Language: Verilog
License (GitHub): GPL-3.0

GitHub data as of 2026-11-10

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Evidence

Observed: Code, documentation and a demo observed; no download method found.
Checked: 2026-11-08

How evidence classes are assigned

Requirements & limits

Prerequisites: The repository supplies raw Verilog files for integration into an FPGA project or simulation wrapper.
Testing evidence: The core is marked 0.9.1-alpha; the author reports a complete match on the standard Z80 tests available to them.
Limits: Source comments are currently in Russian.
License: GPL-3.0 license.

Cite

BibTeX

@misc{z80-silicon-rtl-case,
  title = {{Z80 NMOS Silicon-to-RTL CPU Core: reconstructing transistor logic in Verilog}},
  howpublished = {\url{https://github.com/dr-Titus/z80-silicon-rtl}},
  url = {https://github.com/dr-Titus/z80-silicon-rtl},
  urldate = {2026-11-06},
  note = {Awesome REA entry: \url{https://awesomerea.org/resources/z80-silicon-rtl-case/}}
}

Plain text

Z80 NMOS Silicon-to-RTL CPU Core: reconstructing transistor logic in Verilog. https://github.com/dr-Titus/z80-silicon-rtl (accessed 2026-11-06). Awesome REA entry: https://awesomerea.org/resources/z80-silicon-rtl-case/

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Primary sources

README.md GitHub · dr-Titus/z80-silicon-rtl · Revision 53759f2