# Z80 NMOS Silicon-to-RTL CPU Core: reconstructing transistor logic in Verilog

> Z80 NMOS Silicon-to-RTL CPU Core reconstructs the Zilog NMOS Z80 processor as synchronous Verilog from a transistor-level netlist and successive logic schematics. The author reports testing a Verilator model with Z80 software suites in EmuStudio.

- Type: Case study
- Targets: Firmware
- Category: Independent reconstruction cases
- Relationship: Independent reconstruction project
- Sources reviewed: 2026-11-06
- Added to the catalog: 2026-11-08
- Original resource: <https://github.com/dr-Titus/z80-silicon-rtl>
- Primary source: <https://github.com/dr-Titus/z80-silicon-rtl/blob/53759f204a92818f8fba0d4972d1c980da2c404f/README.md>
- Catalog page: <https://awesomerea.org/resources/z80-silicon-rtl-case/>
- Record JSON: <https://awesomerea.org/resources/z80-silicon-rtl-case/record.json>
- Chinese version: [简体中文](https://awesomerea.org/zh/resources/z80-silicon-rtl-case/index.md)

## Requirements & limits

- **Prerequisites:** The repository supplies raw Verilog files for integration into an FPGA project or simulation wrapper.
- **Testing evidence:** The core is marked 0.9.1-alpha; the author reports a complete match on the standard Z80 tests available to them.
- **Limits:** Source comments are currently in Russian.
- **License:** GPL-3.0 license.

## Primary sources

1. <https://github.com/dr-Titus/z80-silicon-rtl/blob/53759f204a92818f8fba0d4972d1c980da2c404f/README.md>

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## About this entry

The description was reviewed against primary sources.
Original editorial content: MIT. Linked projects, papers and assets retain their own rights and licenses.