{
  "added_at": "2026-11-09",
  "additional_evidence_urls": [
    "https://github.com/14sea/Cyclone_CRAM_Mapper/blob/221f790286eda0bb47e03080c6f7ab0e72377bb6/results/FINDINGS.md",
    "https://github.com/14sea/Cyclone_CRAM_Mapper/blob/221f790286eda0bb47e03080c6f7ab0e72377bb6/LICENSE"
  ],
  "category": "reconstruction-cases",
  "class": "hardware",
  "description_en": "EP4CE6 Bitstream Reverse Engineering maps the proprietary .rbf configuration format of the Cyclone IV EP4CE6F17C8 FPGA. Its Python pipeline compiles controlled Verilog variants with Quartus, diffs bitstreams and records CRAM, LUT and routing mappings. The repository includes format findings and code for reading and writing bitstream features.",
  "description_zh": "EP4CE6 Bitstream Reverse Engineering 研究 Cyclone IV EP4CE6F17C8 FPGA 的 .rbf 配置格式。Python 流程用 Quartus 编译受控 Verilog 变体，比较比特流，记录 CRAM、LUT 和布线映射；仓库还提供格式研究结果及比特流读写代码。",
  "entry_url": "https://awesomerea.org/resources/cyclone-cram-mapper-case/",
  "entry_url_zh": "https://awesomerea.org/zh/resources/cyclone-cram-mapper-case/",
  "evidence_url": "https://github.com/14sea/Cyclone_CRAM_Mapper/blob/221f790286eda0bb47e03080c6f7ab0e72377bb6/README.md",
  "group": "cases",
  "id": "cyclone-cram-mapper-case",
  "json_url": "https://awesomerea.org/resources/cyclone-cram-mapper-case/record.json",
  "kind": "case-study",
  "markdown_url": "https://awesomerea.org/resources/cyclone-cram-mapper-case/index.md",
  "markdown_url_zh": "https://awesomerea.org/zh/resources/cyclone-cram-mapper-case/index.md",
  "name": "EP4CE6 Bitstream Reverse Engineering: mapping Cyclone IV configuration bits",
  "name_zh": "EP4CE6 Bitstream Reverse Engineering：映射 Cyclone IV 配置位",
  "record_type": "resource",
  "relationship": "independent-reconstruction",
  "requirement_facets": [
    "prerequisites",
    "prerequisites",
    "license"
  ],
  "requirements": [
    "Research hardware includes an EP4CE6F17C8 FPGA board and USB-Blaster JTAG programmer.",
    "The documented workflow uses Quartus Prime 21.1 Lite, Python 3 and SQLite.",
    "Code is GPL-3.0-or-later; research data and documentation are CC-BY-SA-4.0."
  ],
  "requirements_zh": [
    "研究硬件包括 EP4CE6F17C8 FPGA 开发板和 USB-Blaster JTAG 下载器。",
    "文档中的流程使用 Quartus Prime 21.1 Lite、Python 3 和 SQLite。",
    "代码采用 GPL-3.0-or-later；研究数据和文档采用 CC-BY-SA-4.0。"
  ],
  "targets": [
    "firmware"
  ],
  "url": "https://github.com/14sea/Cyclone_CRAM_Mapper",
  "verification": "source-reviewed",
  "verified_at": "2026-11-06"
}