# EP4CE6 Bitstream Reverse Engineering: mapping Cyclone IV configuration bits

> EP4CE6 Bitstream Reverse Engineering maps the proprietary .rbf configuration format of the Cyclone IV EP4CE6F17C8 FPGA. Its Python pipeline compiles controlled Verilog variants with Quartus, diffs bitstreams and records CRAM, LUT and routing mappings. The repository includes format findings and code for reading and writing bitstream features.

- Type: Case study
- Targets: Firmware
- Category: Independent reconstruction cases
- Relationship: Independent reconstruction project
- Sources reviewed: 2026-11-06
- Added to the catalog: 2026-11-09
- Original resource: <https://github.com/14sea/Cyclone_CRAM_Mapper>
- Primary source: <https://github.com/14sea/Cyclone_CRAM_Mapper/blob/221f790286eda0bb47e03080c6f7ab0e72377bb6/README.md>
- Catalog page: <https://awesomerea.org/resources/cyclone-cram-mapper-case/>
- Record JSON: <https://awesomerea.org/resources/cyclone-cram-mapper-case/record.json>
- Chinese version: [简体中文](https://awesomerea.org/zh/resources/cyclone-cram-mapper-case/index.md)

## Requirements & limits

- **Prerequisites:** Research hardware includes an EP4CE6F17C8 FPGA board and USB-Blaster JTAG programmer.
- **Prerequisites:** The documented workflow uses Quartus Prime 21.1 Lite, Python 3 and SQLite.
- **License:** Code is GPL-3.0-or-later; research data and documentation are CC-BY-SA-4.0.

## Primary sources

1. <https://github.com/14sea/Cyclone_CRAM_Mapper/blob/221f790286eda0bb47e03080c6f7ab0e72377bb6/README.md>
2. <https://github.com/14sea/Cyclone_CRAM_Mapper/blob/221f790286eda0bb47e03080c6f7ab0e72377bb6/results/FINDINGS.md>
3. <https://github.com/14sea/Cyclone_CRAM_Mapper/blob/221f790286eda0bb47e03080c6f7ab0e72377bb6/LICENSE>

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## About this entry

The description was reviewed against primary sources.
Original editorial content: MIT. Linked projects, papers and assets retain their own rights and licenses.